1. Field of the Invention
Generally, the present disclosure relates to highly sophisticated integrated circuits, including transistors having three-dimensional channel architecture, such as FinFETs, and to a manufacturing method thereof capable of improving the electrical characteristics of the transistor.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel and separated therefrom by a thin insulating layer. The conductivity of the channel, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain, which is also referred to as channel length.
In view of further device scaling based on well-established materials, new transistor configurations have been proposed in which a “three-dimensional” architecture is provided in an attempt to obtain a desired channel width, while at the same time superior controllability of the current flow through the channel is preserved. To this end, so-called FinFETs have been proposed in which a thin sliver or fin of silicon is formed in a thin active layer of an SOI (silicon-on-insulator) or a standard silicon substrate, wherein, on both sidewalls and, if desired, on a top surface, a gate dielectric material and a gate electrode material are provided, thereby realizing a multiple gate transistor whose channel may be fully depleted.
In some conventional approaches for forming FinFETs, the fins are formed as elongated device features followed by the deposition of the gate electrode materials, possibly in combination with any spacers, and thereafter the end portions of the fins may be “merged” by epitaxially growing a source or drain material. In particular, several FinFETs can be connected in parallel in this manner, in order to increase the total drive current. Usually then, in order to realize such parallel connection, the individual FinFETs use the same source and/or drain region.
This, however, has a negative effect on the electrical performances of the FinFET transistors. Among various problems, such an approach with a common source and drain for all FinFETs increases parasitic capacitances between the source and the gate, as well as between the drain and the gate, and it limits the stress type and amount thereof that can be obtained on each of the FinFETs.
In view of the situation described above, the present disclosure relates to semiconductor devices and manufacturing techniques in which FinFETs, or generally three-dimensional transistors, may be formed and potentially connected in parallel to each other while avoiding or at least reducing the effect of one or more of the problems identified above.